The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Referring now to FIG. 1, a functional block diagram of an exemplary memory 50 is shown. Memory 50 includes a controller 52 and charge storage cells 54. Each of the charge storage cells 54 may be capable of storing a range of different charge levels. The range of charge levels may be segmented into two or more mutually exclusive regions. For example, a charge level below a threshold value may be considered an un-programmed state, while a charge level above the threshold value is considered a programmed state.
In some memory applications, two bits may be stored as four charge level regions. For example, a charge storage cell containing 25% or less of a maximum charge level may be considered to be in an un-programmed state. A charge level between 25% and 50% of the maximum charge level corresponds to a first programmed state, between 50% and 75% corresponds to a second programmed state, and between 75% and 100% corresponds to a third programmed state.
Changing the charge level causes a change in threshold voltage. The threshold voltage may be determined by measuring current when a given bias voltage is applied. The amount of current then indicates the charge level, and thus the programmed state. Programmed states may alternatively be defined by ranges of threshold voltages instead of by ranges of charge levels.
As programming and erasing operations are performed on certain ones of the charge storage cells 54, and as time passes, charge levels in others of the charge storage cells 54 may vary. For instance, programming one of the charge storage cells 54 may slightly impact the charge level of an adjacent one of the charge storage cells 54. Likewise, erasing may affect adjacent ones of the charge storage cells 54. Further, charge may leak with the passage of time, causing charge levels to decrease.
Referring now to FIG. 2, a flowchart depicts steps performed in refreshing the charge storage cells 54. The charge storage cells 54 may be periodically refreshed to maintain programmed charge levels. Control may begin upon power-on of the memory 50. Control begins in step 70, where a timer is started. Control continues in step 72, where control determines whether the timer period has expired. If the timer period has expired, control transfers to step 74; otherwise, control remains in step 72.
The timer period may be set to the minimum amount of time in which a charge level of one of the charge storage cells 54 could decay to the upper or lower boundary of its current programmed state. Beyond this period of time, the charge level of one of the charge storage cells 54 may shift from the current programmed state to another programmed state. To prevent this from happening, the charge storage cells 54 are refreshed before the expiration of the timer period.
In step 74, values from the charge storage cells 54 are read. Control continues in step 76, where the charge storage cells 54 are erased. Control continues in step 78, where the values originally read from the charge storage cells 54 are rewritten. Control continues in step 80, where the timer is reset. Control then returns to step 72.
The method of FIG. 2 is similar to that performed by a dynamic random access memory (DRAM) controller. In a DRAM controller, values are read out of memory cells before charge leakage could cause values to be read erroneously. For example, memory cells containing charge may leak to the point where they are indistinguishable from memory cells without charge. The read values are then reprogrammed into the memory cells, where they will be readable for another period of time. A refresh is performed after each time period.